A GROWING REFERENCE FOR DV ENGINEERS
Real DV engineering, worked all the way through.
Register verification, memory allocation, SoC reuse patterns, and firmware verification -- four series that each work one testbench problem area all the way through, with real code, not a tutorial or a listicle.
TOP ARTICLES
SERIES
20 articles across 4 series
01
CSR Verification
A practical series on verifying control and status registers with UVM RAL, beyond what the built-in sequences catch, and the patterns real SoC projects need.
5 ARTICLES
02
Memory Allocation Manager
Using UVM's built-in region allocator for shared memory across block, subsystem, and SoC testbenches, and where the built-in class needs a wrapper to actually scale.
5 ARTICLES
03
SoC Reuse Patterns
The testbench architecture problems that show up specifically when a block-level environment has to survive being integrated into a subsystem and then a full SoC.
5 ARTICLES
04
Firmware Verification
The firmware-on-RTL problems that only show up at multi-core and regression scale: races existing debug tools can't localize, a message-ID logging scheme built to replace UART streaming, and what survives the jump to emulation, post-silicon, and SoC integration.
5 ARTICLES
More series, over time
This grid grows as new topics get written up.
PROJECTS
Working code, not just writing