Projects

Real, runnable code that goes with the writing above, not just articles.

SV & UVM TODAY · CSR NEXT

brokenbench

A growing set of real interview and practice problems across SystemVerilog, UVM, and register-map (CSR) verification, ziglings/rustlings-style. Fix the class or write it from scratch, a checker tells you unambiguously whether you got it right -- including several genuine, currently-open Verilator bugs found and confirmed while building it.